february 2006 FDS8884 n-channel powertrench ? mosfet ?2006 fairchild semiconductor corporation FDS8884 rev. a www.fairchildsemi.com 1 FDS8884 n-channel powertrench ? mosfet 30v, 8.5a, 23m ? general descriptions this n-channel mosfet has been designed specifically to improve the overall efficien cy of dc/dc converters using either synchronous or co nventional switching pwm controllers. it has been optimized for low gate charge, low r ds(on) and fast switching speed. features ? max r ds(on) = 23m ? at v gs = 10v, i d = 8.5a ? max r ds( on ) = 30m ? at v gs = 4.5v, i d = 7.5a ? low gate charge ? 100% r g tested ? rohs compliant l e a d f r e e m t a e l n t i o m p e n i mosfet maximum ratings t a = 25c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 30 v v gs gate to source voltage 20 v i d drain current continuous (note 1a) 8.5 a pulsed 40 a e as single pulse avalanche energy (note 2) 32 mj p d power dissipation 2.5 w derate above 25 o c20mw/ o c t j , t stg operating and storage temperature -55 to 150 o c r ja thermal resistance, junction to ambient (note 1a) 50 o c/w r ja thermal resistance, junction to case (note 1) 25 o c/w device marking device package reel size tape width quantity FDS8884 FDS8884 so-8 330mm 12mm 2500 units 4 3 2 1 5 6 7 8 s d s s so-8 d d d g
FDS8884 n-channel powertrench ? mosfet FDS8884 rev. a www.fairchildsemi.com 2 electrical characteristics t j = 25c unless otherwise noted off characteristics on characteristics (note 3) dynamic characteristics switching characteristics (note 3) drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0v 30 v ? bv dss ? t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 o c 23 mv/ o c i dss zero gate voltage drain current v ds = 24v 1 a v gs = 0v t j = 125 o c250 i gss gate to source leakage current v gs = 20v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 1.2 1.7 2.5 v ? v gs(th) ? t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 o c -4.9 mv/ o c r ds( on ) drain to source on resistance v gs = 10v, i d = 8.5a, 19 23 m ? v gs = 4.5v , i d = 7.5a, 23 30 v gs = 10v, i d = 8.5a, t j = 125 o c 26 32 c iss input capacitance v ds = 15v, v gs = 0v, f = 1mhz 475 635 pf c oss output capacitance 100 135 pf c rss reverse transfer capacitance 65 100 pf r g gate resistance f = 1mhz 0.9 1.6 ? t d(on) turn-on delay time v dd = 15v, i d = 8.5a v gs = 10v, r gs = 33 ? 510ns t r rise time 918ns t d(off) turn-off delay time 42 68 ns t f fall time 21 34 ns q g total gate charge v ds = 15v, v gs = 10v i d = 8.5a 9.2 13 nc q g total gate charge v ds = 15v, v gs = 5v i d = 8.5a 5.0 7 nc q gs gate to source gate charge 1.5 nc q gd gate to drain charge 2.0 nc v sd source to drain diode voltage i sd = 8.5a 0.9 1.25 v i sd = 2.1a 0.8 1.0 v t rr reverse recovery time i f = 8.5a, di/dt = 100a/ s 33 ns q rr reverse recovery charge 20 nc notes: 1: r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the s older mounting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user?s board design. 2: starting t j = 25 c, l = 1mh, i as = 8a, v dd = 27v, v gs = 10v. 3: pulse test:pulse width <300 s, duty cycle <2% . b) 105 c/w when mounted on a .04 in 2 pad of 2 oz copper minimun pad c) 125 c/w when mounted on a scale 1 : 1 on letter size paper a) 50c/w when mounted on a 1 in2 pad of 2 oz copper
FDS8884 n-channel powertrench ? mosfet FDS8884 rev. a www.fairchildsemi.com 3 typical characteristics t j = 25c unless otherwise noted figure 1. on region characteristics 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 10 20 30 40 v gs = 4.5v v gs = 3v v gs = 3.5v v gs = 4.0v v g s = 5.0v v g s = 10v pulse duration = 80 p s duty cycle = 0.5%max v ds , drain to source voltage (v) i d , drain current (a) figure 2. 5 10152025303540 0.5 1.0 1.5 2.0 2.5 3.0 normalized drain to source on-resistance i d , drain current(a) v gs = 3v v gs = 10v v gs = 5v v gs = 4.5v v gs = 4v v gs = 3.5v pulse duration = 80 p s duty cycle = 0.5%max normalized on-resistance vs drain current and gate voltage figure 3. normalized -80 -40 0 40 80 120 160 0.6 0.8 1.0 1.2 1.4 1.6 i d = 8.5a v gs = 10v t j , junction temperature ( o c ) normalized drain to source on-resistance on resistance vs junction temperature figure 4. 246810 15 20 25 30 35 40 45 50 55 60 t j = 25 o c t j = 150 o c i d = 8.5a pulse duration = 80 p s duty cycle = 0.5%max v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) on-resistance vs gate to source voltage figure 5. transfer characteristics 12345 0 5 10 15 20 25 30 35 40 v dd = 5v t j = -55 o c t j = 25 o c t j = 150 o c pulse duration = 80 p s duty cycle = 0.5%max v gs , gate to source voltage (v) i d , drain current (a) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1e-3 0.01 0.1 1 10 v sd , body diode forward voltage (v) i s , reverse drain current (a) t j = -55 o c t j = 25 o c t a = 150 o c v gs = 0v 40 source to drain diode forward voltage vs source current
FDS8884 n-channel powertrench ? mosfet FDS8884 rev. a www.fairchildsemi.com 4 figure 7. 0246810 0 2 4 6 8 10 v dd = 20v v dd = 10v v gs , gate to source voltage(v) q g , gate charge(nc) v dd = 15v gate charge characteristics figure 8. 0.1 1 10 100 200 300 400 500 600 700 f = 1mhz v gs = 0v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss 30 capacitance vs drain to source voltage figure 9. unclamped inductive switching capability 0.01 0.1 1 10 1 10 20 starting t j = 125 o c starting t j = 25 o c i as , avalanche current(a) 20 t av , time in avalanche(ms) figure 10. 25 50 75 100 125 150 0 1 2 3 4 5 6 7 8 9 v gs = 10v v gs = 4.5v i d , drain current (a) t a , ambient temperature ( o c ) r t ja = 50 o c /w maximum continuous drain current vs ambient temperature figure 11. 0.1 1 10 100 0.01 0.1 1 10 100 dc 1s 100ms 10ms 1ms 100us 10us i d , drain current (a) v ds , drain to source voltage (v) operation in this area may be limited by r ds(on) single pulse t j = max rated t a = 25 o c forward bias safe operating area figure 12. single pulse maximum power dissipation 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 1 10 100 1000 v gs =10v single pulse t, pulse width (s) p (pk) , peak transient power ( w ) 2000 t a = 25 o c i = i 25 for temperatures above 25 o c derate peak current as follows: 150 t a ? 125 ----------------------- - typical characteristics t j = 25c unless otherwise noted
10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 1e-3 0.01 0.1 1 normalized thermal impedance, z t ja t, rectangular pulse duration(s) d = 0.5 0.2 0.1 0.05 0.02 0.01 single pulse duty cycle-descending order 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a FDS8884 n-channel powertrench ? mosfet FDS8884 rev. a www.fairchildsemi.com 5 figure 13. transient thermal response curve typical characteristics t j = 25c unless otherwise noted
FDS8884 rev. a www.fairchildsemi.com 6 FDS8884 n-channel powertrench ? mosfet trademarks the following are registered and unregistered trademarks fairchil d semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve re liability, function or design. fairchild does not assume any liability arising out of the application or u se of any product or circuit described herein; neither does it convey any license under it s patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or s ystems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, c an be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms acex? activearray? bottomless? build it now? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? fact? fact quiet series? fast ? fastr? fps? frfet? globaloptoisolator? gto? hisec? i 2 c? i-lo ? implieddisconnect ? intellimax? isoplanar? littlefet? microcoupler? microfet? micropak? microwire? msx ? msxpro ? ocx ? ocxpro ? optologic ? optoplanar? pacman? pop? power247? poweredge? powersaver? powertrench ? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure ? rapidconnect ? serdes ? scalarpump ? silent switcher ? smart start? spm? stealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tcm? tinylogic ? tinyopto? trutranslation? uhc? ultrafet ? unifet? vcx? wire? across the board. around the world. ? the power franchise ? programmable active droop? datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. spec ifications may change in any manner without notice. preliminary first production this datas heet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. no identification needed full production this datas heet contains final spec ifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i18
|
